Logic Synthesis and Verification
Hardware and Petri nets: application to asynchronous circuit design
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
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This paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed method iteratively performs Boolean decomposition of each such gate F into a two-input combinational or sequential gate G available in the library and two gates H1 and H2 simpler than F, while preserving the original behavior and speed-independence of the circuit. To extract functions for H1 and H2 the method uses Boolean relations as opposed to the less powerful algebraic factorization approach used in previous methods. After logic decomposition, the overall library matching and optimization is carried out. Logic resynthesis, performed after speed-independent signal insertion for H1 and H2, allows for sharing of decomposed logic. Overall, this method is more general than the existing techniques based on restricted decomposition architectures, and thereby leads to better results in technology mapping