Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Billion-Transistor Architectures
Computer
Computer
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Adaptive mode control: A static-power-efficient cache design
ACM Transactions on Embedded Computing Systems (TECS)
Simultaneous multithreading
IBM Journal of Research and Development
Computer Architecture Techniques for Power-Efficiency
Computer Architecture Techniques for Power-Efficiency
Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
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Power efficiency of microprocessor is essential to green computing. As most microprocessors become multi-core and multi-thread, it's important to study low power design for them. The architecture of MCMT, a multi-core multi-thread microprocessor, is described briefly in this paper. Several low power design techniques, including fine-grained clock gating, instruction throttling and adaptive L2 cache are presented to reduce both the dynamic power and the leakage power. Experimental results show that the presented techniques can meet the power constraints.