OOPSLA '87 Conference proceedings on Object-oriented programming systems, languages and applications
Application system/400 performance characteristics
IBM Systems Journal
Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
DAISY: dynamic compilation for 100% architectural compatibility
Proceedings of the 24th annual international symposium on Computer architecture
Fast, effective code generation in a just-in-time Java compiler
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Scalable cross-module optimization
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
The Jalapeño dynamic optimizing compiler for Java
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
From system F to typed assembly language
ACM Transactions on Programming Languages and Systems (TOPLAS)
A hardware mechanism for dynamic extraction and relayout of program hot spots
Proceedings of the 27th annual international symposium on Computer architecture
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Relational profiling: enabling thread-level parallelism in virtual machines
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
On the importance of points-to analysis and other memory disambiguation methods for C programs
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
rePLay: A Hardware Framework for Dynamic Optimization
IEEE Transactions on Computers
An instruction set and microarchitecture for instruction level distributed processing
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Managing multi-configuration hardware via dynamic working set analysis
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Java Language Specification, Second Edition: The Java Series
Java Language Specification, Second Edition: The Java Series
Ensuring code safety without runtime checks for real-time control systems
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Billion-Transistor Architectures
Computer
FX!32: A Profile-Directed Binary Translator
IEEE Micro
Automatic pool allocation for disjoint data structures
Proceedings of the 2002 workshop on Memory system performance
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Memory safety without runtime checks or garbage collection
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
A provably sound TAL for back-end optimization
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Proceedings of the 30th annual international symposium on Computer architecture
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Proceedings of the 30th annual international symposium on Computer architecture
A Programmable Co-processor for Profiling
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
POWER4 system microarchitecture
IBM Journal of Research and Development
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Proceedings of the 32nd annual international symposium on Computer Architecture
Vector LLVA: a virtual vector instruction set for media processing
Proceedings of the 2nd international conference on Virtual execution environments
Decomposing the load-store queue by function for power reduction and scalability
IBM Journal of Research and Development
Secure virtual architecture: a safe execution environment for commodity operating systems
Proceedings of twenty-first ACM SIGOPS symposium on Operating systems principles
Running a Java VM inside an operating system kernel
Proceedings of the fourth ACM SIGPLAN/SIGOPS international conference on Virtual execution environments
Lightweight module isolation for sensor nodes
Proceedings of the First Workshop on Virtualization in Mobile Computing
Supporting adaptive application mobility
OTM'07 Proceedings of the 2007 OTM Confederated international conference on On the move to meaningful internet systems - Volume Part II
Relax: an architectural framework for software recovery of hardware faults
Proceedings of the 37th annual international symposium on Computer architecture
Petri-nets as an intermediate representation for heterogeneous architectures
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part II
GPU fluids in production: a compiler approach to parallelism
ACM SIGGRAPH 2011 Talks
Proceedings of the 27th Annual ACM Symposium on Applied Computing
Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Generation of TLM testbenches using mutation testing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Scaling symbolic execution using ranged analysis
Proceedings of the ACM international conference on Object oriented programming systems languages and applications
Using likely invariants for automated software fault localization
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
Scaling symbolic execution using staged analysis
Innovations in Systems and Software Engineering
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A virtual instruction set architecture (V-ISA) implementedvia a processor-specific software translation layercan provide great flexibility to processor designers. Recentexamples such as Crusoe and DAISY, however, haveused existing hardware instruction sets as virtual ISAs,which complicates translation and optimization. In fact,there has been little research on specific designs for a virtualISA for processors. This paper proposes a novel virtualISA (LLVA) and a translation strategy for implementingit on arbitrary hardware. The instruction set is typed,uses an infinite virtual register set in Static Single Assignmentform, and provides explicit control-flow and dataflowinformation, and yet uses low-level operations closelymatched to traditional hardware. It includes novel mechanismsto allow more flexible optimization of native code,including a flexible exception model and minor constraintson self-modifying code. We propose a translationstrategy that enables offline translation and transparent offlinecaching of native code and profile information, whileremaining completely OS-independent. It also supports optimizationsdirectly on the representation at install-time,runtime, and offline between executions. We show experimentallythat despite its rich information content,virtual object code is comparable in size to native machinecode, virtual instructions expand to only 2-4 ordinaryhardware instructions on average, and simple translationcosts under 1% of total execution time except for veryshort runs.