The connection machine
Dynamic path-based branch correlation
Proceedings of the 28th annual international symposium on Microarchitecture
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
S/390 cluster technology: Parallel Sysplex
IBM Systems Journal
In search of clusters (2nd ed.)
In search of clusters (2nd ed.)
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Scalable Shared-Memory Multiprocessing
Scalable Shared-Memory Multiprocessing
Billion-Transistor Architectures
Computer
Global wiring on a wire routing machine
DAC '82 Proceedings of the 19th Design Automation Conference
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Blue Gene: a vision for protein science using a petaflop supercomputer
IBM Systems Journal - Deep computing for the life sciences
Some observations based on simple models of MP scaling
ISPASS '00 Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
40 years later .... a new engine to handle an operating system infrastructure
ACM SIGARCH Computer Architecture News
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Trends in lithography and process technology indicate that billion-transistor computer chips will be possible well before the end of the decade. Such a large number of transistors could be used to implement dynamic learning techniques to improve the performance of a processor for many applications. However, the efficiency of use of transistors in this manner is not high. A more attractive use of the available transistors is to bring more of the entire system onto the chip, and this paper examines two different approaches for doing so. The first involves bringing memory closer to the processors in a symmetric multiprocessor cell, and using these cells in a regular organization with a programmable interconnection to create powerful computers. The second involves integration on the same chip of varied structures such as processors, DRAM, sensors, and transducers, which in the past required different processing capabilities-commonly referred to as the System-on-a-Chip approach. The paper describes the exciting options offered by both approaches and discusses the implications of each for programming and tool development.