Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration

  • Authors:

  • Basavaraj Talwar;Shailesh Kulkarni;Bharadwaj Amrutur

  • Affiliations:

  • -;-;-

  • Venue:
  • VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
  • Year:
  • 2009

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Abstract

This paper presents a low-power LDPC decoder design for additive white Gaussian noise (AWGN) channels. The proposed decoding scheme provides constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It ...