CAFES: A framework for intrachip application modeling and communication architecture design
Journal of Parallel and Distributed Computing
On the design space exploration through the Hellfire Framework
Journal of Systems Architecture: the EUROMICRO Journal
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In order to fulfill the increasing performance requirements, complex embedded systems design makes use of many processors communicating through efficient infrastructures, performing Multiprocessor-Systems-on-Chip (MPSoCs). Issues related to execution time and energy consumption estimations become more relevant during the design stage of such systems, in order to verify their compliance with the specification. Different estimation techniques have been proposed, including analytical and simulation-based methods. Analytical methods are faster than simulation-based methods, but the system description is more complex, and sometimes this approach conducts to low precision results misleading future design steps. On the other hand, the more accurate results achieved with simulation-based method, using low-level descriptions, may delay the design making it unfeasible or at least affecting the time-to-market. In this context, improvements in simulation-based methods become pertinent. This paper presents a study, a design flow and a tool for high-level simulation-based estimation of execution time and energy consumption of homogeneous MPSoCs. The implemented tool, which employs the methodology presented in this paper, improved dramatically simulation times when compared to RTL simulations. The preliminary results show that, for some cases, the RTL simulation takes tens hours while the implemented tool gets close estimation results in just few seconds.