×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clustered NOC, a suitable design for group communications in Network on Chip
Computers and Electrical Engineering
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In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asynchronous. These types of cores provide native flow control that is compatible with this network, thus reducing adapter overhead and buffering needs by applying backpressure directly to the sending core. We show that under realistic traffic patterns our sample network meets performance requirements and uses less power compared to a similar design. This concept of a simplified network, along with latency insensitive cores lends itself well to meeting the needs of low-power interconnect components in future design processes.