On convex formulation of the floorplan area minimization problem
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Floorplan sizing by linear programming approximation
Proceedings of the 37th Annual Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear programming-based algorithm for floorplanning in VLSI design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer planning as an Integral part of floorplanning with consideration of routing congestion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplan considering interconnection between different clock domains
ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11
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This paper analyses the floorplanning methods based on linear programming and presents a linear replacement of the non-linear objective function. It also presents the sub-section linearization method to replace the original nonlinear items in the constraint inequalities. Compared with former floorplanning methods based on linear programming, the solutions of the method in this paper always lie in the feasible region of the original floorplanning problem. Experimental results show that the method in this is competitive.