Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
FAR: fixed-points addition & relaxation based placement
Proceedings of the 2002 international symposium on Physical design
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
APlace: a general analytic placement framework
Proceedings of the 2005 international symposium on Physical design
mFAR: fixed-points-addition-based VLSI placement algorithm
Proceedings of the 2005 international symposium on Physical design
Floorplan design for multi-million gate FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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In this paper, a new timing-driven placement algorithm is proposed to handle complicated placement requirements inherent in FPGAs with heterogeneous resources (dedicated logic block, memory block). The new algorithm employs a multi-layer density system with each layer modeling a drastically different architectural resource. By introducing the multi-layer density system, a heterogeneous placement task is translated to a set of homogeneous ones, with each of them being handled at a different density layer. We also present a new iterative timing optimization scheme which is seamlessly integrated in the placement process. The tight interaction between the placement and timing optimization produces superior timing results for industrial designs.