Acceleration of random-walk-based linear circuit analysis using importance sampling

  • Authors:
  • Tetsuro Miyakawa;Koh Yamanaga;Hiroshi Tsutsui;Hiroyuki Ochi;Takashi Sato

  • Affiliations:
  • Kyoto University, Kyoto, Japan;Murata Manufacturing Co. Ltd., Kanagawa, Japan;Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan

  • Venue:
  • Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
  • Year:
  • 2011

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Abstract

This paper proposes an importance sampling (IS) technique based on quasi-zero-variance estimation for accelerating convergence of random-walk-based power grid analysis. In our approach, the alternative probability for IS is incrementally updated after every Mr samples of random walk so that more recent and thus more accurate node voltages are utilized to asymptotically achieve ideal zero-variance estimation. We also propose a method to determine efficient Mr for the r-th probability update; although smaller Mr results more aggressive update of alternative probability, the alternative probability becomes inaccurate if Mr is too small. The estimation error of the proposed method decreases O((M/r)-r/2), which breaks O(M-1/2), the slow convergence-rate barrier of normal Monte Carlo analysis. Our trial implementation achieved 790x speedup compared with a conventional random-walk-based circuit analysis for analyzing IBM power grid benchmark circuits at 1mV accuracy.