On-chip power supply noise and its implications on timing

Authors:
Lars J. Svensson;Johnny Pihl;Daniel A. Andersson;Per Larsson-Edefors
Affiliations:
Chalmers University of Technology, Göteborg, Sweden;Atmel Norway AS, Trondheim, Norway;Atmel Norway AS, Trondheim, Norway;Chalmers University of Technology, Göteborg, Sweden
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

Citing 3
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Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

We address two problems of assessing the influence of power- supply variations on timing analysis. We present a method to assign a supply-dependent hold margin; and we describe a method to accurately characterize logic gates for the sen- sitivity of delay on supply-voltage variations. We use a com- mercial microcontroller as a design example.