A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Method to Estimate Slew and Delay in Coupled Digital Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Noise Model for Multiple Segmented Coupled RC Interconnects
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Efficient Gate Delay Modeling for Large Interconnect Loads
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
With the technology scaling and shrinking feature sizes, coupling noise has become one of the most critical concerns in today's interconnect-centric design, especially for long global buses. A very common consequence of coupling is that the output signal waveform becomes non-monotonic. Traditionally, only through circuit simulation can the output waveform can be precisely acquired. However, this method suffers from low efficiency especially for today's super scale circuits. This paper proposes a fast algorithm to accurately estimate the output waveform for buses at the presence of coupling noise. Experimental results show that only a little more than 2% mean error is induced while, on average, the running time of the proposed algorithm is 23 times faster than HSPICE simulation.