FastHenry: a multipole-accelerated 3-D inductance extraction program
DAC '93 Proceedings of the 30th international Design Automation Conference
Least Squares Support Vector Machine Classifiers
Neural Processing Letters
ALPS: the age-layered population structure for reducing the problem of premature convergence
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Design and Analysis of Experiments
Design and Analysis of Experiments
Robust CMOS micromachined inductors with structure supports for Gilbert mixer matching circuits
IEEE Transactions on Circuits and Systems II: Express Briefs
A mathematical steady-state design model for fully-integrated boost and buck DC---DC converters
Analog Integrated Circuits and Signal Processing
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Variability-Aware Multilevel Integrated Spiral Inductor Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The evolution of computer-aided design tools has extended the capabilities of a designer by pushing the optimality of complex circuits beyond the ad hoc manual implementation. This work presents a framework to co-optimize the circuit and the layout parameters of fully integrated inductive DC---DC converters. The framework comprises expensive optimization that is speeded up by active learning sample selection and evolutionary techniques to acquire an optimal converter. A tapered inductor topology is used to increase the quality of the on-chip inductor and to improve the efficiency of the overall monolithic DC---DC converter. The optimization framework is validated by co-optimizing the design parameters and the tapered inductor layout for a fully-integrated DC---DC boost converter in a 0.13 μm CMOS technology. The power loss in the circuit is reduced with 27 % resulting in a 7 % efficiency improvement, compared to a fully-integrated DC---DC boost converter with a regular inductor topology.