Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switch-factor based loop RLC modeling for efficient timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Timing uncertainty caused by inductive and capacitivecoupling is one of the major bottlenecks in timing analysis. In thispaper, we propose an effective loop RLC modeling technique toefficiently decouple lines with both inductive and capacitivecoupling. We generalize the RLC decoupling problem based ontransmission line theory and a switch-factor, which is the voltageratio between two nets. This switch-factor is also known as theMiller factor and is widely used to model capacitive coupling.The proposed modeling technique can be directly applied to partialRLC netlists extracted using existing parasitic extraction toolswithout advance knowledge of the return path. The new modelaccurately captures the impact of neighboring switching activitywhen it significantly affects the size of current return loop. Asdemonstrated in our experiments, the new model accuratelypredicts both upper and lower delay bounds as a function ofneighboring switching patterns. Therefore, this approach can beeasily implemented into existing timing analysis flows such asmax-timing and min-timing analysis. Finally, we apply the newmodeling approach to a range of activities across the designprocess including timing optimization, static timing analysis, highfrequency clock design, and data-bus wire planning.