Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis

Authors:
Luca Ramini;Paolo Grani;Sandro Bartolini;Davide Bertozzi
Affiliations:
University of Ferrara, Ferrara, Italy;University of Siena, Siena, Italy;University of Siena, Siena, Italy;University of Ferrara, Ferrara, Italy
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

Citing 8
Cited 0

The M5 Simulator: Modeling Networked Systems

IEEE Micro
On the Design of a Photonic Network-on-Chip

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

IEEE Transactions on Computers
The PARSEC benchmark suite: characterization and architectural implications

Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Re-architecting DRAM memory systems with monolithically integrated silicon photonics

Proceedings of the 37th annual international symposium on Computer architecture
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

Proceedings of the Conference on Design, Automation and Test in Europe
Multi-Optical Network-on-Chip for Large Scale MPSoC

IEEE Embedded Systems Letters
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints

NOCS '12 Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip

Quantified Score

Hi-index	0.00

Visualization

Abstract

Optical networks-on-chip (ONoCs) are currently still in the concept stage, and would benefit from explorative studies capable of bridging the gap between abstract analysis frameworks and the constraints and challenges posed by the physical layer. This paper aims to go beyond the traditional comparison of wavelength-routed ONoC topologies based only on their abstract properties, and for the first time assesses their physical implementation efficiency in an homogeneous experimental setting of practical relevance. As a result, the paper can demonstrate the significant and different deviation of topology layouts from their logic schemes under the effect of placement constraints on the target system. This becomes then the preliminary step for the accurate characterization of technology-specific metrics such as the insertion loss critical path, and to derive the ultimate impact on power efficiency and feasibility of each design.