Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Penelope: The NBTI-Aware Processor
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking
Proceedings of the conference on Design, automation and test in Europe
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
Alleviating NBTI-induced failure in off-chip output drivers
Proceedings of the great lakes symposium on VLSI
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NBTI-aware design of NoC buffers
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip
Sensor-wise methodology to face NBTI stress of NoC buffers
Proceedings of the Conference on Design, Automation and Test in Europe
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture
Proceedings of the 50th Annual Design Automation Conference
Employing circadian rhythms to enhance power and reliability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NBTI mitigation by optimized NOP assignment and insertion
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture levels. In this paper, we propose a multi-level optimization approach, combining techniques at the circuit and microarchitecture levels, for reducing the impact of NBTI on the functional units (FUs) of a high-performance processor core. We perform SPICE simulations to evaluate the impact of circuit-level design optimizations to reduce the NBTI guardband in terms of area, delay, and power. We then propose a set of NBTI-aware dynamic instruction scheduling policies at the microarchitecture level and quantify their impact on application performance and guardband reduction through execution-driven simulation. We show that carefully combining techniques at both these levels provides the most attractive solution to reducing the guardband while imposing the least overhead in terms of area, power, delay, and application performance.