Analog automatic test pattern generation for quasi-static structural test

  • Authors:
  • Amir Zjajo;José Pineda De Gyvez

  • Affiliations:
  • NXP Semiconductors, Eindhoven, The Netherlands;NXP Semiconductors, Eindhoven, The Netherlands and Eindhoven University of Technology, Eindhoven, The Netherlands

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2009

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Abstract

A new approach for structural, fault-oriented analog test generation methodology to test for the presence of manufacturing-related defects is proposed. The output of the test generator consists of optimized test stimuli, fault coverage and sampling instants that are sufficient to detect the failure modes in the circuit under test. The tests are generated and evaluated on a multistep ADC taking into account the potential fault masking effects of process spread on the faulty circuit responses. Similarly, the test generator results offer indication for the circuit partitioning within the framework of circuit performance, area and testability.