Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

Authors:
S. J. Spinks;C. D. Chalk;I. M. Bell;M. Zwolinski
Affiliations:
Zarlink Semiconductor, Cheney Manor, Swindon, Wiltshire, SN2 2QW, UK. Stephen_Spinks@zarlink.com;Philips Semiconductors, 2nd Avenue, Millbrook Ind. Est, Southampton, Hampshire, SO15 0DJ, UK. Chris.Chalk@philips.com;Department of Engineering, University of Hull, Cottingham Road, Hull, HU6 7RX, UK. I.M.Bell@hull.ac.uk;School of Electronics & Computer Science, University of Southampton, Highfield, Southampton, SO17 1BJ, UK. mz@ecs.soton.ac.uk
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2004

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Abstract

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.