Logic testing and design for testability
Logic testing and design for testability
FSPICE: a tool for fault modelling in MOS circuits
Integration, the VLSI Journal
Fault simulation of linear analog circuits
Journal of Electronic Testing: Theory and Applications - Joint special issue on analog and mixed-signal testing
Creating A Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program Development
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Rapid frequency-domain analog fault simulation under parameter tolerances
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fault Modeling and Simulation Using VHDL-AMS
Analog Integrated Circuits and Signal Processing - Special issue: Analog VHDL
A Behavior Model for Next Generation Test Systems
Journal of Electronic Testing: Theory and Applications
Defect-Oriented Experiments in Fault Modelling and Fault Simulation of Microsystem Components
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Analogue Fault Modelling and Simulation for Supply Current Monitoring
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A new quality estimation methodology for mixed-signal and analogue ICs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
The Test Requirements Model (TeRM) Communicating Test Information Throughout the Product Life Cycle
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations
Journal of Electronic Testing: Theory and Applications
TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation
Journal of Electronic Testing: Theory and Applications
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A simulation-based methodology for test program verification is presented. Executing test programs on a virtual test system allows simulation of Device Under Test (DUT) behavior. Simulating both device and test hardware and software allows test engineers to check and debug test programs without fabricated devices. It results in a gain of time and permits design and test to occur concurrently. This also yields better overall circuit testability. Our effort concerns development of Automatic Testing Equipment (ATE) model and software interfaces to link the simulator with both design tools and test tools. Further, we propose extending the general fault simulation concept to analog world. Fault models are suggested and tools for fault simulation automation have been developed. They include fault list generation, simulation control and result analysis as well.