Analog system verification in the presence of parasitics using behavioral simulation
DAC '93 Proceedings of the 30th international Design Automation Conference
Testing of analog systems using behavioral models and optimal experimental design techniques
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
System-level design for test of fully differential analog circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multifrequency Analysis of Faults in Analog Circuits
IEEE Design & Test
Analogue Fault Simulation Based on Layout-Dependent Fault Models
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Inductive Contamination Analysis (ICA) with SRAM Application
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Fault Modeling for the Testing of Mixed Integrated Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Defect-oriented test methodology for complex mixed-signal circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Automatic test vector generation for mixed-signal circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Architecture of a testable analog fuzzy logic controller
IEEE Transactions on Fuzzy Systems
Modeling of VLSI RC parasitics based on the network reduction algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.01 |
Parametric fault modeling methodology based on statistical process simulation is proposed. Statistical simulation based on process disturbances allows to avoid testing for faults which are unlikely to occur. As a result, the number of tests required to verify the circuit's performance is reduced. A practical example with results measured on prototype chips is presented.