Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Analogue Fault Simulation Based on Layout-Dependent Fault Models
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Fault Modeling for the Testing of Mixed Integrated Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On Accurate Modeling and Efficient Simulation of CMOS Opens
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Fast, robust DC and transient fault simulation for nonlinear analogue circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Towards design and validation of mixed-technology SOCs
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
The Implementation of a VHDL-AMS to SPICE Converter
Journal of VLSI Signal Processing Systems - Mixed-signal design issues
The Implementation of a VHDL-AMS to SPICE Converter
Analog Integrated Circuits and Signal Processing - Special issue on mixed-signal design issues
Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation
Analog Integrated Circuits and Signal Processing
An operational amplifier model for evaluating test strategies at behavioural level
Microelectronics Journal
Automated model generation algorithm for high-level fault modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal approach for specification-driven AMS behavioral model generation
Proceedings of the Conference on Design, Automation and Test in Europe
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Fault simulation is an accepted part of the test generationprocedure for digital circuits. With complex analog and mixed-signalintegrated circuits, such techniques must now be extended. Analog simulationis slow and fault simulation can be prohibitively expensive because of thelarge number of potential faults. We describe how the number of faults to besimulated in an analog circuit can be reduced by fault collapsing, and howthe simulation time can be reduced by behavioral modeling of fault-free andfaulty circuit blocks. These behavioral models can be implemented in SPICEor in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS doespotentially offer advantages in tackling this problem, but there are anumber of computational difficulties to be overcome.