The Implementation of a VHDL-AMS to SPICE Converter

Authors:
Shenggao Li;Brian Okoon;Mona Hella;Mohammed Ismail;Maya Rubeiz
Affiliations:
2015 Neil Avenue, Dreese Lab 205, Analog VLSI Lab, The Ohio State University;2015 Neil Avenue, Dreese Lab 205, Analog VLSI Lab, The Ohio State University;2015 Neil Avenue, Dreese Lab 205, Analog VLSI Lab, The Ohio State University;2015 Neil Avenue, Dreese Lab 205, Analog VLSI Lab, The Ohio State University&semi/ Radio Electronics Lab, Royal Institute of Technology, Kista-Stockolm, Sweden;Air Force Research Laboratory/Information Directorate, Wright-Patterson AFB, OH
Venue:
Analog Integrated Circuits and Signal Processing - Special issue on mixed-signal design issues
Year:
1999

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Abstract

The implementation of a VHDL-AMS to SPICE converter(Vhdl2Spice) to be inserted in a complete CAD environment [1] isdescribed. Vhdl2Spice generates a SPICE netlist by tracing down theVHDL IIR parse tree available from the already existing VHDLanalyzer. Corresponding to each VHDL design unit, the output of theconverter is represented as a subcircuit in SPICE. By doing so, thehierarchical characteristic of VHDL is retained in the SPICErepresentation; hence future extension to both programs can be madein parallel. The Vhdl2Spice converter is also a demonstration of theextensibility of the AIRE [2] for a complete integration of VHDL-AMSwith other CAD tools.