Macromodeling with SPICE
Challenges and advances in electrical interconnect analysis (tutorial)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
IEEE Spectrum
Analog and mixed-signal hardware description languages
The Designer's Guide to VHDL
VHDL for Simulation, Synthesis, and Formal Proofs of Hardware
VHDL for Simulation, Synthesis, and Formal Proofs of Hardware
Mixed-Mode Simulation and Analog Multilevel Simulation
Mixed-Mode Simulation and Analog Multilevel Simulation
Applications of VHDL to Circuit Design
Applications of VHDL to Circuit Design
VHDL: Toward a Unified View of Design
IEEE Design & Test
The Implementation of a VHDL-AMS to SPICE Converter
Journal of VLSI Signal Processing Systems - Mixed-signal design issues
The Implementation of a VHDL-AMS to SPICE Converter
Analog Integrated Circuits and Signal Processing - Special issue on mixed-signal design issues
Behavioral synthesis of field programmable analog array circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Hardware description languages (HDL) such as VHDL are today anessential technology to support most of the steps of digital hardwaredesign, such as simulation, synthesis, testing, and formal proof. As theIEEE 1076 standard, VHDL is committed to evolve through five yearsre-standardization cycles whose objective is to make the necessary languagechanges or extensions in response to feedbacks from users and from toolsuppliers. Requirements to support analog and mixed-signal systems have beenissued during the initial phases of the second VHDL re-standardizationcycle. Due to the complexity of the topic, a separate IEEE working group,referenced as 1076.1, was formally formed in 1993 with the charter toprovide a language proposal based on VHDL 1076 that includes these newrequirements. The language design phase is now complete and a solid languagearchitecture is defined. A formal IEEE balloting process to approve theproposal as the new IEEE Standard 1076.1 has started in August 1997 and willbe completed before the end of the year. This paper presents an overview ofthe 1076.1 language proposal that enhances VHDL to handle systems thatexhibit continuous behavior over time and over amplitude. The way it isdesigned, VHDL 1076.1 will support the description and the simulation ofboth non-conservative and conservative continuous and mixed discrete/continuous systems.