Behavioral modeling of transmission gates in VHDL
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An intermediate representation for behavioral synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An introduction to the Research Queueing Package
WSC '85 Proceedings of the 17th conference on Winter simulation
Integrating stochastic performance analysis with system design tools
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Simulation with GPSS and Gpssv
Simulation with GPSS and Gpssv
IEEE Design & Test
VHSIC hardware description (VHDL) development program
DAC '83 Proceedings of the 20th Design Automation Conference
Analog and Mixed-Signal Extensions to VHDL
Analog Integrated Circuits and Signal Processing - Special issue: Analog VHDL
Hardware-accelerated components for hybrid computing systems
Proceedings of the 2008 compFrame/HPC-GECO workshop on Component based high performance
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A high-level view of the relevance of and relationships between key events in the development of the very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) is presented. Three phases in the life cycle of the language, the definition, development, and deployment phases, are outlined. The concept of a design information space, a convenient abstraction for categorizing various VHDL efforts and understanding their interrelationships, is introduced. Two representative VHDL examples dealing with performance modeling and testing are discussed. The waveform and vector exchange specification (WAVES) VHDL subset for the exchange of waveform descriptions is described.