The VHDL Handbook
A VHDL Standard Package for Logic Modeling
IEEE Design & Test
A Minimalist Approach to VHDL Logic Modeling
IEEE Design & Test
VHDL: Toward a Unified View of Design
IEEE Design & Test
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WAVES, which stands for waveform and vector exchange specification, is a way to represent in text the histories of logic signals and the requirements placed on them. It is intended to serve as a way of exchanging information between simulator and tester environments. A description is given of the WAVES event-value concept, which captures both the logic value sets used in simulation and the pin codes used in contemporary test-vector languages. The encoding waveforms and frames are discussed.