Behavioral modeling of transmission gates in VHDL

Authors:
S. S. Leung
Affiliations:
Department of Electrical Engineering, Michigan State University, East Lansing, MI
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

Citing 2
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Abstract

This paper presents a technique for describing the behavior of transmission gates (TGs) in VHDL. The concept of virtual signal is introduced into the TG's data structure to represent the nature of the connection. The model's semantics are coded in three parts: the state transition, the steady states, and the connecting protocol. Simulation results indicate that the model is correct and robust.