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Programmable-weight building blocks for analog VLSI neural network processors
Analog Integrated Circuits and Signal Processing
Analog and Mixed-Signal Extensions to VHDL
Analog Integrated Circuits and Signal Processing - Special issue: Analog VHDL
Design Approaches to Field-Programmable Analog Integrated Circuits
Analog Integrated Circuits and Signal Processing - Special issue on field programmable analog arrays
A Novel Switched-Capacitor Based Field-Programmable Analog Array Architecture
Analog Integrated Circuits and Signal Processing - Special issue on field programmable analog arrays
A Switched Capacitor Approach to Field-Programmable Analog Array (FPAA) Design
Analog Integrated Circuits and Signal Processing - Special issue on field programmable analog arrays
DPAD2—A Field Programmable Analog Array
Analog Integrated Circuits and Signal Processing - Special issue on field programmable analog arrays
The EPAC Architecture: An Expert Cell Approach to Field Programmable Analog Devices
Analog Integrated Circuits and Signal Processing - Special issue on field programmable analog arrays
A Current Conveyor based Field Programmable Analog Array
Analog Integrated Circuits and Signal Processing - Special issue on field programmable analog arrays
A Current-Mode based Field-Programmable Analog Array for Signal Processing Applications
Analog Integrated Circuits and Signal Processing - Special issue on field programmable analog arrays
A High-Frequency Field-Programmable Analog Array (FPAA) Part 1: Design
Analog Integrated Circuits and Signal Processing - Special issue on field programmable analog arrays
Technology mapping and retargeting for field-programmable analog arrays
DATE '00 Proceedings of the conference on Design, automation and test in Europe
FAAR: A Router for Field-Programmable Analog Arrays
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Mapping algorithm for large-scale field programmable analog array
Proceedings of the 2005 international symposium on Physical design
Flexibility-oriented design methodology for reconfigurable ΔΣ modulators
Proceedings of the conference on Design, automation and test in Europe
Design of a window comparator with adaptive error threshold for online testing applications
Microelectronics Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Placement for large-scale floating-gate field-programable analog arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This article presents methods to translate a behavioral-level analog description into a Field Programmable Analog Array (FPAA) implementation. The methods consist of several steps that are referred to as function decomposition, macrocell synthesis, placement and routing, and postplacement simulation. The focus of this article is on the first three steps. The function decomposition step deals with decomposing a high-order system function into a set of lower-order functions. We present an efficient procedure for searching for an optimal solution. This procedure is based on first formally demonstrating the equivalence of two previously used optimization criteria. The objective of the macrocell synthesis step is to generate a hardware realization. A modified signal flow graph is introduced to represent FPAA circuits and graph transformations are used to identify the realizations that comply with the FPAA hardware constraints. The modified signal flow graph also allows scaling of capacitor values due to the limited set of allowable values in an FPAA. For the placement and routing step, an efficient method to estimate the circuit performance degradation due to parasitic effects is given. Using performance degradation as the cost function, an algorithm for finding an optimal FPAA placement and routing configuration is given. The efficacy of the methods developed is demonstrated by direct measurements on a set of filters.