Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Behavioral partitioning in the synthesis of mixed analog-digital systems
Proceedings of the 38th annual Design Automation Conference
Behavioral synthesis of field programmable analog array circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Configurable analog signal processing
Digital Signal Processing
IEEE Transactions on Circuits and Systems II: Express Briefs
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Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first placement algorithm for large-scale floating-gate-based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. Our FPAAclustering algorithm first groups analog components into a set of clusters so that the total number of routing switches used is minimized and all IO paths are balanced in terms of routing switches used. Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage and balance again. Experimental results demonstrate the effectiveness of our approach.