A field-programmable mixed-analog-digital array
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
ARCHGEN: automated synthesis of analog systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
KIR—a graph-based model for description of mixed analog/digital systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Behavioral synthesis of analog systems using two-layered design space exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Technology mapping and retargeting for field-programmable analog arrays
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low-Noise Electronic System Design
Low-Noise Electronic System Design
Library Binding for High-Level Synthesis of Analog Systems
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Mapping algorithm for large-scale field programmable analog array
Proceedings of the 2005 international symposium on Physical design
Deterministic approaches to analog performance space exploration (PSE)
Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Circuits and Systems II: Express Briefs
Placement for large-scale floating-gate field-programable analog arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. In this paper, we investigate the issues in mixed-signal behavioral partitioning and design space exploration for signal-processing systems. We begin with the system behavior specified in an intermediate format called the Mixed Signal Flow Graph, based on the time-amplitude characterization of signals. We present techniques for analog-digital behavioral partitioning of the MSFG, and performance estimation of the technology-mapped analog and digital circuits. The partitioned solution must satisfy constrants on imposed by the target field programmable mixed-signal architecture on avaialable configurable resources, available data converters, their resolution and speed, and IO pins. The quality of the solution is evaluated based on two metrics, namely feasibility and performance. The former is a measure of the validity of the solution with respect to the architectural constraints. The latter measures the performance of the system based on bandwidth/speed and noise.