Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Technology mapping and retargeting for field-programmable analog arrays
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Behavioral partitioning in the synthesis of mixed analog-digital systems
Proceedings of the 38th annual Design Automation Conference
Behavioral synthesis of field programmable analog array circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FAAR: A Router for Field-Programmable Analog Arrays
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
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Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With these advances, analog circuits and systems can be programmable, reconfigurable, adaptive, implemented on standard CMOS to take advantage of scaled CMOS technology, and at a density comparable to digital memories. Our goal in this paper is to develop the first physical design automation toolset for floating-gate based FPAA with focus on minimization of parasitic effects on FPAA interconnect. We provide graph-based analog circuit and FPAA device modeling suitable for efficient mapping. Our FPAA clustering algorithm constructs Computational Analog Blocks (CAB) from analog circuit elements while improving the utilization of the device and reducing its impact on the total number of routing switches used. Experimental results demonstrate the effectiveness of our approach.