Macromodeling of the A.C. characteristics of CMOS Op-amps
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fault Modeling and Simulation Using VHDL-AMS
Analog Integrated Circuits and Signal Processing - Special issue: Analog VHDL
Fault Macromodeling for Analog/Mixed-Signal Circuits
Proceedings of the IEEE International Test Conference
An operational amplifier model for evaluating test strategies at behavioural level
Microelectronics Journal
Automated model generation algorithm for high-level fault modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
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One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.