Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Multi-VDD Testing for Analog Circuits
Journal of Electronic Testing: Theory and Applications
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction
Journal of Electronic Testing: Theory and Applications
Analog circuit test based on a digital signature
Proceedings of the Conference on Design, Automation and Test in Europe
Generating test data for specification-based tests via quasirandom sequences
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
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In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits