An introduction to support Vector Machines: and other kernel-based learning methods
An introduction to support Vector Machines: and other kernel-based learning methods
Specification Test Compaction for Analog Circuits and MEMS
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Non-RF to RF Test Correlation Using Learning Machines: A Case Study
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Specification-driven test generation for analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prediction of analog performance parameters using fast transient testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nonlinear decision boundaries for testing analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Several existing methodologies have leveraged the correlation between the non-RF and the RF performances of a circuit in order to predict the latter from the former and, thus, reduce test cost. While this form of specification test compaction eliminates the need for expensive RF measurements, it also comes at the cost of reduced test accuracy, since the retained non-RF measurements and pertinent correlation models do not always suffice for adequately predicting the omitted RF measurements. To alleviate this problem, we explore several methodologies that estimate the confidence in the obtained test outcome. Subsequently, devices for which this confidence is insufficient are retested through the complete specification test suite. As we demonstrate on production test data from a zero-IF down-converter fabricated at IBM, the proposed methodologies overcome the inability of standard specification test compaction methods to reach industrially acceptable test quality levels, and enable efficient exploration of the tradeoff between test accuracy and test cost.