Analytical fault modeling and static test generation for analog ICs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fault-based automatic test generator for linear analog circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Parametric fault simulation and test vector generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Functional Fault Models for Analog Circuits
IEEE Design & Test
Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis
Proceedings of the IEEE International Test Conference
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations
Journal of Electronic Testing: Theory and Applications
Evaluation of Signature-Based Testing of RF/Analog Circuits
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical tolerance analysis using statistical behavioral models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assessment of Microfluidic System Testability using Fault Simulation and Test Metrics
Journal of Electronic Testing: Theory and Applications
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A new approach for analog fault modeling and simulation is presented. The proposed approach utilizes the sensitivity of the circuit's DC node voltages to the process variations and consequently the current deviance so as to differentiate the faulty behavior. A systematic method is proposed for the fault discrimination to minimize the probability that the circuit is accepted as a fault-free when it is faulty. Tests are generated and evaluated taking into account the potential fault masking effects of process spread on the faulty circuit responses. The introduced fault model is validated on a time-interleaved sample-and-hold circuit. Simulation results demonstrate the effectiveness of the model.