Hierarchical tolerance analysis using statistical behavioral models

• Authors: T. Koskinen;P. Y.K. Cheung
• Venue: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Year: 2006

A methodology is presented for deriving statistical models of analog and digital circuit cells at the behavioral level. These models can be combined in a single simulation environment for efficient yield estimation of large circuits. The motivation is the growing importance of mixed analog/digital ASICs and the impracticality of traditional approaches to tolerance analysis based on computationally intensive device-level simulation. An efficient method of mapping from device-level space to behavioral space which requires no a priori assumption about the analytical mapping is presented. The method is demonstrated using an operational amplifier example. By combining the mapping with statistical methods, tolerance information is included in the behavioral model. A statistical model giving the mean, standard deviation, and correlation of behavioral parameters is obtained. Hence the tolerance analysis problem can be defined at the behavioral level of simulation and the statistical behavioral models combined to estimate the variation of system level performance. This hierarchical methodology is demonstrated using a two-stage flash analog-to-digital converter circuit. Compared to device-level simulation, a fifteen-fold gain in efficiency, and accuracy to within 2% were achieved in the yield estimate using a static performance specification