DRAFTS: discretized analog circuit fault simulator
DAC '93 Proceedings of the 30th international Design Automation Conference
A comprehensive fault macromodel for opamps
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fault macromodeling and a testing strategy for opamps
Journal of Electronic Testing: Theory and Applications
Neural Networks: A Comprehensive Foundation
Neural Networks: A Comprehensive Foundation
Fault Modeling for the Testing of Mixed Integrated Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Hierarchical tolerance analysis using statistical behavioral models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper; we propose an eflcient fault macro-modelingtechnique for analog/mixed-signal circuits. Weformulate the fault macromodeling problem as a problemof deriving the macro parameter set B based on the performanceparameter set P of the transistor-level faultycircuit. The fault macromodel is intended to be used forefJicient macro-level fault simulation. In such applications,a common approach to speeding up the macro-modelingprocess is to generate a large number of datapairs (e B) (the training set) and interpolate an empiricalmapping function B=F(P) based on the training set.In our technique, generation of each data pair requiresonly one run of macro-level simulation, as opposed tomultiple runs of macro-level simulation required by iterativefault macromodeling techniques. We also propose across-correlation-based technique to select a subset ofparameters from the high dimensional parameter set P tospeed up function interpolation. We demonstrate theeffectiveness and efficiency of our proposed fault macro-modelingtechnique by showing some preliminary experimentalresults on an industnal design.