ARCHGEN: automated synthesis of analog systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Asymptotic probability extraction for non-normal distributions of circuit performance
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Hierarchical analysis of process variation for mixed-signal systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Hierarchical tolerance analysis using statistical behavioral models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic fault detection and the selection of measurements for analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation
Journal of Electronic Testing: Theory and Applications
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Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this article, we present a hierarchical variance analysis methodology for multistage analog circuits. Starting from the process/layout level, we derive implicit hierarchical relations and extract the sensitivity information analytically. We make use of previously computed values whenever possible so as to reduce computational time. The proposed approach is particularly geared for the domain of design and test automation, where multiple runs on slightly different circuits are necessary. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.