Fault-based automatic test generator for linear analog circuits
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DAC '97 Proceedings of the 34th annual Design Automation Conference
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Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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IEEE Design & Test
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VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose a methodology for adaptive modeling of analog/RF circuits. This modeling technique is specifically geared towards evaluating the response of a faulty circuit in terms of its specifications and/or measurements. The goal of this modeling approach is to compute important test metrics, such as fail probability, fault coverage, and/or yield coverage of a given measurement under process variations. Once the models for the faulty and fault-free circuit are generated, we can simply use Monte-Carlo sampling (as opposed to Monte-Carlo simulations) to compute these statistical parameters with high accuracy. We use the error budget that is defined in terms of computing the statistical metrics and the position of the threshold(s) to decide how precisely we need to extract the necessary models. Experiments on LNA and Mixer confirm that the proposed techniques can reduce the number of necessary simulations by factor of 7 respectively, in the computation of the fail probability.