Evaluation of analog/RF test measurements at the design stage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical parametric test metrics estimation: a ΣΔ converter BIST case study
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Defect-based test optimization for analog/RF circuits for near-zero DPPM applications
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.03 |
Radio-frequency (RF) test cost is soaring due to the increasing complexity of RF devices. Radically new test approaches that enable test time reduction while ensuring product quality are needed to reduce the overall product cost. In this paper, we present a test development methodology for RF circuits based on novel parametric, open-circuit, and short-circuit defect models. We inject parametric defects as deviations in physical circuit parameters, such as resistances, transistor widths, and lengths, and inject open- and short-circuit defects into the critical locations that are derived from the layout using inductive fault analysis. Despite fault injection, we consider a circuit unacceptable only if it violates any one of the performance specifications. Our test development method aims at reducing not only the number of measurements but also the overall test hardware cost by incorporating the relative setup cost of each measurement into our selection criteria. Experimental results on an RF front-end device show that our test methodology reduces the test time by 50% and the number of test setups by 17% while identifying all unacceptable circuit instances with a 99% failure coverage without any yield loss.