Parametric fault simulation and test vector generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Industrial Relevance of Analog IFA: A Fact or a Fiction
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical Test Compaction Using Binary Decision Trees
IEEE Design & Test
Evaluation of analog/RF test measurements at the design stage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect-Oriented Testing of RF Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously proposed Built-In Self-Test (BIST) technique for ΣΔ Analog-to-Digital Converters (ADC) explaining in detail the derivation of a behavioral model that captures the main nonidealities in the circuit. The estimated test metrics are further analyzed in order to uncover trends in a large device sample that explain the source of erroneous test decisions.