Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fault Modeling for the Testing of Mixed Integrated Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Practical Implementation of Defect-Oriented Testing for a Mixed-Signal Class-D Amplifier
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
Defect Screening Using Independent Component Analysis on I_DDQ
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Non-RF to RF Test Correlation Using Learning Machines: A Case Study
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect-Oriented Testing of RF Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Analog circuits are often tested based on their specifications. While specification-based testing ensures the initial product quality, full testing is often not possible in high volume production. Moreover, even full specification-based testing cannot guarantee that the circuit does not contain any physical defects. Some application domains require near-zero defect levels independent of whether the specifications are met. In this work, we present a defect based test optimization method focusing on defective parts per million (DPPM) minimization. We extract potential defects through inductive fault analysis (IFA) and reduce the number of tests without degrading the test quality. In order to achieve near zero DPPM, we employ outlier analysis to identify defective circuits that cannot be identified using specification based methods. Simulation results on an LNA show that DPPM is reduced down to 0 at a cost of 0.2% yield loss with the proposed method.