Fast Fault Simulation for Nonlinear Analog Circuits

Authors:
Nur Engin;Hans G. Kerkhoff
Affiliations:
-;-
Venue:
IEEE Design & Test
Year:
2003

Citing 7
Cited 2

Fundamentals of computer-aided circuit simulation

Fundamentals of computer-aided circuit simulation
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast, robust DC and transient fault simulation for nonlinear analogue circuits

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Efficient DC fault simulation of nonlinear analog circuits

Proceedings of the conference on Design, automation and test in Europe
Analog and Mixed-Signal Benchmark Circuits-First Release

Proceedings of the IEEE International Test Conference
Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

EDTC '95 Proceedings of the 1995 European conference on Design and Test
On the Fault-Injection-Caused Increase of the DAE-Index in Analogue Fault Simulation

ETW '99 Proceedings of the 1999 IEEE European Test Workshop

A tool for single-fault diagnosis in linear analog circuits with tolerance using the T-vector approach

VLSI Design
Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation

Journal of Electronic Testing: Theory and Applications

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Abstract

A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.