Fault simulation of linear analog circuits
Analog Integrated Circuits and Signal Processing - Joint special issue on analog and mixed-signal testing.
Homotopy techniques for obtaining a DC solution of large-scale MOS circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Rapid frequency-domain analog fault simulation under parameter tolerances
DAC '97 Proceedings of the 34th annual Design Automation Conference
The Designer's Guide to Spice and Spectre
The Designer's Guide to Spice and Spectre
DC Built-In Self-Test for Linear Analog Circuits
IEEE Design & Test
Industrial Relevance of Analog IFA: A Fact or a Fiction
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fast, robust DC and transient fault simulation for nonlinear analogue circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Fault Simulation for Analog Circuits Under Parameter Variations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Fast Fault Simulation for Nonlinear Analog Circuits
IEEE Design & Test
7.1 Nonlinear Analog DC Fault Simulation by One-Step Relaxation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Speed-up of High Accurate Analog Test Stimulus Optimization
ITC '99 Proceedings of the 1999 IEEE International Test Conference
TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation
Journal of Electronic Testing: Theory and Applications
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This paper describes a method to improve the efficiency of nonlinear DC fault simulation. The method uses the Newton-Raphson algorithm to simulate each faulty circuit. The key idea is to order the given list of faults in such a way that the solution of previous faulty circuit can serve as a good initial point for the simulation of the next faulty circuit. To build a good ordering, one step Newton-Raphson iteration is performed for all the faulty circuits once, and the results are used to quantify how faulty circuits and the good circuit are close in their behaviors. With one-step Newton-Raphson iteration implemented by Householder's formula, the proposed method has virtually no overhead. Experimental results on a set of 36 MCNC benchmark circuits show an average speedup of 4.4 and as high as $15$ over traditional stand-alone fault simulation.