Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits

Efficient DC fault simulation of nonlinear analog circuits

Proceedings of the conference on Design, automation and test in Europe

An approach to realistic fault prediction and layout design for testability in analog circuits

Proceedings of the conference on Design, automation and test in Europe

On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages

Journal of Electronic Testing: Theory and Applications

Digital Window Comparator DfT Scheme for Mixed-Signal ICs

Journal of Electronic Testing: Theory and Applications

Static and Dynamic On-Chip Test Response Evaluation Using a Two-Mode Comparator

ETW '00 Proceedings of the IEEE European Test Workshop

17.2 A Design for Testability Study on a High Performance Automatic Gain Control Circuit

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Test Metrics for Analog Parametric Faults

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Built-in loopback test for IC RF transceivers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems