Design of robust test criteria in analog testing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Defining Cost Functions for Robust IC Design and Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Journal of Electronic Testing: Theory and Applications
An evolutionary approach for worst-case tolerance design
Engineering Applications of Artificial Intelligence
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A yield maximization methodology, called the linearized performance penalty (LPP) method, that uses a penalty function as its objective is introduced. The penalty function formulation allows the integration of the goals of circuit performance improvement and yield maximization. It is computationally efficient since the objective function can be evaluated with the computational effort of about one circuit simulation. Also, a simple, yet effective, method to account for operating point variations is introduced. The effectiveness of the LPP method is illustrated through several circuit examples