Analog automatic test pattern generation for quasi-static structural test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Block-level Bayesian diagnosis of analogue electronic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...