Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A general framework for spatial correlation modeling in VLSI design
Proceedings of the 44th annual Design Automation Conference
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Buffered clock tree synthesis for 3D ICs under thermal variations
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Pre-bond testable low-power clock tree design for 3D stacked ICs
Proceedings of the 2009 International Conference on Computer-Aided Design
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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3D integration has new manufacturing and design challenges such as timing corner mismatch between tiers and device variation due to Through Silicon Via (TSV) induced stress. Timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers. TSV induced stress is another challenge in 3D Clock Tree Synthesis (CTS). Mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. In this paper, we propose clock tree design methodology with the following objectives: (a) to minimize clock period variation by assigning optimal z-location of clock buffers with an Integer Linear Program (ILP) formulation, (b) to prevent unwanted skew induced by the stress. In the results, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with our robust 3D CTS.