IEEE Transactions on Computers
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Proceedings of the 2007 international symposium on Physical design
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation
Proceedings of the Conference on Design, Automation and Test in Europe
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Manufacturing process corner, voltage and temperature (PVT) conditions lead to variation in path delays and clock skews. Such variations end up degrading the performance of manufactured chips. Since, such variations are hard to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. These buffers are tuned to maximize operating clock frequency of a design. In this paper, we report a study on using measured delays on selected patterns to determine which buffers should be targeted for tuning. Based on statistical simulation studies, it is found that the proposed approach can improve clock frequency by as much as 9% in the average case.