Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
A Power Management Methodology for High-Level Synthesis
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Resource Allocation and Binding Approach for Low Leakage Power
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Better than optimum?: register reduction using idle pipelined functional units
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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A large fraction of the total power dissipated in a digital circuit is consumed by the clocked elements in the data-path. Hence, savings in power usage of these components can be directly reflected in a circuit's overall power consumption. Reducing power through techniques that optimize power consumption in combinational elements has been extensively discussed in the existing literature. However, these techniques cannot be applied for reducing the power in sequential elements. In this work, we focus on this problem, and introduce a novel cluster-based register optimization technique that is employed in High-Level Synthesis (HLS) with Power Islands. Our experiments conducted on several synthesis benchmarks implemented at the transistor level using a 65 nm process technology showed anaverage reduction of 18% in total power consumption due to our technique with no or little area overhead.