MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications
Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Dynamic and Aggressive Scheduling Techniques for Power-Aware Real-Time Systems
RTSS '01 Proceedings of the 22nd IEEE Real-Time Systems Symposium
Dynamic Voltage and Cache Reconfiguration for Low Power
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Leakage aware dynamic voltage scaling for real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems
Proceedings of the 2004 international symposium on Low power electronics and design
A Unified Compressed Memory Hierarchy
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Power Analysis of System-Level On-Chip Communication Architectures
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
System-wide energy minimization for real-time tasks: lower bound and approximation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A self-tuning configurable cache
Proceedings of the 44th annual Design Automation Conference
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Cache leakage control mechanism for hard real-time systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme
Proceedings of the 47th Design Automation Conference
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimization of variable-voltage core-based systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy-aware task scheduling with task synchronization for embedded real-time systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Embedded Computing Systems (TECS)
Reachability Analysis of Cost-Reward Timed Automata for Energy Efficiency Scheduling
Proceedings of Programming Models and Applications on Multicores and Manycores
| Hi-index | 0.00 |
System optimization techniques are widely used to improve energy efficiency as well as overall performance. Dynamic voltage scaling (DVS) is well studied and known to be successful in reducing processor energy consumption. Due to the increasing significance of the memory subsystem's energy consumption, dynamic cache reconfiguration (DCR) techniques are recently proposed at the aim of improving cache subsystem's energy efficiency. As the manufacturing technology scales into the order of nanometers, leakage current, which leads to static power consumption, becomes a significant contributor in the overall power dissipation. In this paper, we consider various system components and study their impact on system-wide energy consumption under different processor voltage levels as well as cache configurations. Based on the observation, we efficiently integrate DVS and DCR techniques together to make decisions judiciously so that the total energy consumption is minimized. Our studies show that considering only DVS or DCR and ignoring the impact from other system components may lead to incorrect conclusions in overall energy savings. Experimental results demonstrate that our approach outperforms existing leakage-aware DVS techniques by 47.6% and leakage-oblivious DVS + DCR technique by up to 23.5%.